The present invention relates to digital integrated circuits and more particularly, the present invention relates to an apparatus for minimizing false edges at the input thereof.
Integrated circuits oftentimes receive digital signals from transmission lines. It is known that even though the ideal input signal is a rectangular signal which has straight edges it is known that transmission line signals are noisy. This noise creates complicated shapes of the signal on the transmission line such that there are reflections thereon. Many of these types of transmission signals are so complicated and noisy that glitches can be received at the integrated circuit input. These noisy signals produce false edges which can cause improper circuit operation.
As is generally well known, in order to provide smaller and faster devices in CMOS process technology circuits CMOS devices have been designed which have a reduced scaling or a shrinking of the geometries thereof. For example, the gate length of the devices, which have been around 1.6 microns, are further reduced to under 1 micron so as to achieve higher speeds of operation. In particular, when the effective length of the gate decreases the gate delay will be reduced so as to yield faster devices. However, the shrinking of the sizes of the integrated semiconductor devices to a smaller size has not been accomplished without any resulting problems. Such semiconductor devices of reduced dimensions fail generally from being more noise sensitive (i.e., lower noise immunity) and being not capable of providing reliable data transfer.
One application where noise immunity and reliable data transfer becomes important is in the field of data transmission on a fully loaded Small Computer System Interface (SCSI) bus line which is coupled from a transmission line for communication with small computers. The basic problem encountered when transferring data on the SCSI bus line is due to noise and glitches which may cause double strobing of the data. The glitches are more hazardous when they appear on the request (REQB) and acknowledge (ACKB) lines.
The control signals REQB and ACKB are used to perform a xe2x80x9chandshakexe2x80x9d so as to transfer the data back and forth between a target (i.e., disc drive) and an initiator (i.e., host computer). A glitch occurring in the control signal REQB can cause one or more extra bytes to be counted during long data transfers at the transfer rate of between 1.0-10 Mbytes/sec. On the other hand, the incorrect or wrong data could be transferred such as when an early control signal REQB occurs and the data signal lines are still being settled, thus causing the wrong data to be sampled. In another situation, the glitch present in the control signal REQB when the SCSI phase lines are being switched could result in a wrong phase.
Hence, it is important to develop means to filter out the noise associated with such a signal. There have been previous circuits designed to filter out such noises. However, one of the problems with such circuits is that oftentimes when several glitches or false edges are produced by the transmission line then these false edges can add up to provide a false signal. Therefore, there can be an accumulation of false signals. This accumulation would then appear as one signal which in turn can be viewed as a true edge. Hence, it is important to reduce the chances that a particular series of glitches will look like one true signal.
In addition, if there are a plurality of power supply voltage levels being provided for example, one supply may be 5 volts and a second supply may be 3.3 volts, the rise and fall times of the internal signals associated with prior art devices would be different, thereby causing the filtering to be different. Hence, it is necessary to provide a means to allow for the proper delay times associated with multiple voltage supply levels. One way of addressing the difference in delay for multiple voltages is to change the capacitance sizes on the nodes of the circuit to make them different for one voltage range compared to another. However, by adding capacitors this would increase the size of an integrated circuit and there is a better way to adjust the delay.
Accordingly, what is needed is a circuit to address the above-mentioned problems. More particularly, what is necessary is a circuit that will allow for the rejection of false edges from a transmission line or the like. In addition, the circuit should be one which can be utilized for multiple power supply voltage ranges. Finally, what is needed is a circuit which can operate in a way that if there are multiple false edges in a particular transmission line signal those false edges will not accumulate and appear as a single true edge. The present invention addresses the above described problems.
An apparatus for removing false edges from an input signal comprising: means for receiving the input signal; means coupled to the receiving means for sensing rising and falling edges of the signal; means coupled for passing a rising edge if a first predetermined time period is exceeded before a next falling edge is sensed, passing a falling edge if a second predetermined time period is exceeded before a next rising edge is sensed; the first predetermined time period being longer than the second predetermined time period.
In one aspect of the present invention, the passing means is programmable so as to account for different power supply voltage levels.
In another aspect of the present invention, the apparatus further includes means for reinitializing the voltage therewithin to ensure there is no accumulation of glitches at the output thereof.
Through the use of the present invention false edges are programmably rejected depending upon input from control circuitry. In addition, the present invention allows for false edges to be similarly removed from input signals when the chip uses different power supply voltage levels.